1. Field of the Invention
This invention relates to a method of forming contact windows in semiconductor devices, and more particularly to a method of forming contact windows in wiring-layer patterns in a self-aligning manner.
2. Description of the Related Art
As semiconductor elements becomes smaller and smaller, it gets more difficult to allow design flexibility to the spacing between contact windows and their adjacent wiring layer patterns.
In conventional lithography techniques, it is necessary to take into account aligning allowance for a mask slip between contact windows and wiring patterns as well as allowance for a variation in the contact window diameter, which hinders the more microscopic design of semiconductor devices.
To deal with this problem, what are called self-aligning contact techniques have been developed which separate the wiring patterns from the contact windows by means of a sidewall insulating film formed on the sidewall of the wiring layer patterns.
Some of conventional general self-aligned contact technique have been disclosed in, for example, Published Unexamined Japanese Patent Application No. 2-30124.
Self-aligning contact techniques disclosed in Published Unexamined Japanese Patent Application No. 2-30124 are roughed out as follows.
A polysilicon film and a CVD silicon oxide film are patterned at a time to form a pattern including an internal wiring layer (hereinafter, referred to as a gate) on a silicon substrate. Then, a sidewall insulating film of a CVD silicon oxide film is formed on the sidewall of the pattern. Next, silicon nitride and silicon are sequentially deposited on the substrate to form a silicon nitride film and a polysilicon film. Then, borophosphosilicate glass (hereinafter, referred to as BPSG) is deposited on the polysilicon film to form a BPSG film. Then, photoresist is applied to the BPSG film to form a resist film. Using photolithography techniques, the resist film is then etched to form a resist pattern with windows in it. Next, using REI techniques, the BPSG film is etched with the resist pattern as a mask to form contact windows. At this time, the etching is ceased at the time when the polysilicon film is exposed. Then, the polysilicon is oxidized using thermal oxidation techniques. At this time, the BPSG film is allowed to reflow by heat caused in the oxidation process. The silicon nitride film functions as a barrier layer that stops the progress of oxidation. Then, using RIE techniques, the silicon nitride film and the oxide film formed on the surface of the substrate are removed with the BPSG film as a mask. Next, using sputtering techniques, aluminium alloy is deposited on the substrate to form an aluminum alloy film. Then, the aluminium alloy film is patterned to form a metal wiring layer that is electrically connected to the substrate via contact windows.
The above-mentioned self-aligning contact techniques have the following problems.
After the formation of the sidewall insulating film, the interlayer insulating (the BPSG film) is formed on the substrate. After this, using RIE techniques, the interlayer insulating film is etched to form contact windows in the BPSG film, so that the insulating film having the most important effect on the gate insulating properties, or the sidewall insulating film, is exposed to an etchant used to form contact windows. This thins the sidewall insulating film, which makes it difficult to control the remaining film amount. If the sidewall insulating film becomes thinner too much, there appears an electric leak path between the metal wiring layer and the gate, leading to insulating failure.